The present invention relates generally to the fabrication of integrated circuits, and more particularly to the formation of contacts in an integrated circuit.
Most integrated circuit (IC) manufacturing processes typically include a number of manufacturing steps. Such steps may form, shape or otherwise modify a material, such as a conductive, semiconductive and/or insulating material, and thereby create an IC device.
It can be desirable to reduce the number of steps in a manufacturing process. Such a reduction in process steps may have a number of beneficial results. The complexity of the overall manufacturing process may be reduced, making the fabrication of an IC easier to accomplish. A process yield may be increased, as the elimination of one or more steps may translate into fewer chances of forming defects. An IC may be fabricated in a shorter time period (cycle time is reduced). This can reduce the overall cost and/or increase manufacturing capacity.
The elimination of particular IC manufacturing process steps may have other benefits. For some integrated circuits, it may be desirable to minimize an IC""s exposure to temperature cycles (keeping as small a xe2x80x9cthermal budgetxe2x80x9d as possible). Too many temperature cycles in a fabrication process may undesirably alter properties of structures formed within an IC. As just a few examples, if an IC includes metal-oxide-semiconductor (MOS) field effect transistors (FET), exceeding a thermal budget may result in shifts in the threshold voltage (Vt) of such transistors. The reliability of such transistors may also be adversely affected, as transistor junctions may be more susceptible to failure mechanisms such as junction breakdown or xe2x80x9cpunch-throughxe2x80x9d current.
If an integrated circuit includes metal contacts to a doped semiconductor substrate, temperature cycles may result in higher contact resistance due to segregation of dopants at the metal-semiconductor interface and/or increased oxidation of the metal.
If an integrated circuit includes a substrate with diffusion regions formed with dopants, temperature cycles may increase diffusion region features due to out-diffusion of dopants.
Accordingly, reductions in the number of temperature cycles in an IC manufacturing process may produce more robust devices, avoid higher contact resistance, and/or allow for smaller device features.
Integrated circuits can typically include various layers of conductive and/or semiconductive materials (referred to herein collectively as xe2x80x9cconductingxe2x80x9d materials), as well as insulating materials. For example, an integrated circuit may include a substrate in which a number of active devices (such as transistors) may be formed. Such active devices may then be connected to one another by one or more conducting layers. The interconnecting conducting layers may be separated from one another by insulating layers.
A conducting layer may be formed from a single layer of material, or alternatively, include one or more conducting materials. As just a few examples, such a layer can include a conventionally doped polycrystalline silicon (polysilicon) and xe2x80x9csilicidexe2x80x9d (silicon-metal alloy). Alternatively, a conducting layer may include a titanium(Ti)-tungsten(W) alloy layered onto bulk aluminum, with an underlying barrier layer comprising Ti, Ti-nitride (TiN), or a Ti alloy.
Similarly, insulating layers can also be composites. As just one example, an insulating layer may include a xe2x80x9cdopedxe2x80x9d silicon dioxide (xe2x80x9coxidexe2x80x9d) and an xe2x80x9cundopedxe2x80x9d silicon oxide (undoped silicate glass or xe2x80x9cUSGxe2x80x9d). The doped silicon oxide can include dopant elements, such as boron and phosphorous, while the undoped silicon oxide can be essentially free of dopant elements. Phosphorous doped silicon dioxide (phosphosilicate glass or xe2x80x9cPSGxe2x80x9d) can provide advantageous ion gettering and/or step coverage properties. Boron and phosphorous doped silicon dioxide (borophosphosilicate glass or xe2x80x9cBPSGxe2x80x9d) can also provide such advantages, and can be formed at lower temperatures, and thus can result in a more desirable thermal budget.
An insulating layer may perform a variety of functions in an integrated circuit. For example, an insulating layer may serve to electrically isolate one conducting layer or structure from another. Further, an insulating layer may serve as the surface on which subsequent layers are formed and patterned. Therefore, in many cases it may be desirable for an insulating layer to provide a relatively planar surface.
Different conducting layers may be connected to one another and/or to a substrate by contacts and/or vias. Contacts and/or vias can include contact holes that extend through one or more insulating layers. Conventionally, a contact may connect a conducting portion of a substrate to a conducting layer, while a via may connect two different conducting layers to one another.
A conventional way of forming a contact hole in one or more insulating layers may include lithography and etch steps. Lithography can be used to form an etch pattern over an insulating layer (that includes the location of contact holes). An etch step can transfer the pattern onto one or more lower situated insulating layers.
One concern with certain contact structures can be the alignment of a contact with a lower conducting layer. Because a contact is usually formed by etching a hole through an insulating layer to an underlying conducting layer or structure, it is desirable that an etched hole to be aligned over the desired contact location in the lower conducting layer.
Further, it may be desirable to ensure that a contact hole is sufficiently insulated from other conductive lines. For example, in the case of semiconductor devices having insulated gate field effect transistors (IGFETs), such as metal-oxide-semiconductor FETs (MOSFETs), it is desirable to have a contact hole aligned with a source or drain, but at the same time, be sufficiently insulated from a conducting gate structure. A common approach to aligning contacts to conducting gate structures is a xe2x80x9cself-alignedxe2x80x9d contact. A self-aligned contact may include a lower conducting structure (such as a transistor gate) that includes a top insulating layer and a side insulating layer (such as a xe2x80x9csidewallxe2x80x9d). With such an arrangement, a contact hole can be etched without a minimum spacing requirement with respect to the lower conducting structure.
Another concern regarding, contacts and/or vias is contact area. The area of a contact can be of concern as a substrate on which a contact is formed may also include other important features, such as transistor channels, transistor isolation structures, transistor diffusion regions, and/or device wells. Thus, reductions in contact size can provide more area for other features and/or reduce the overall size of an integrated circuit device. Further, in many processes, contact area may have a minimum requirement in order to ensure a low enough contact resistance value. Thus, it is desirable that a contact forming process be capable of meeting a minimum contact resistance value.
Various factors may contribute to reducing contact area. In the case of xe2x80x9cself-alignedxe2x80x9d contacts, sidewalls and/or other structures, such as xe2x80x9cetchxe2x80x9d stop layers, may encroach on a contact area. Another factor is that of contact aspect ratio (AR). An aspect ratio can describe the ratio between a contact height and width, when viewed in cross section. The higher the aspect ratio, the more difficult it may be to form the contact.
To better understand the formation of certain integrated circuit structures, including contacts structures, a conventional self-aligned contact (SAC) approach is set forth in FIGS. 7A-7H. FIGS. 7A-7H set forth a number of side cross-sectional views of a portion of an integrated circuit.
FIG. 7A shows a substrate 700 on which may be formed conducting structures 702. A conducting structure 702 may be the gate of an insulated gate field effect transistor, such as a MOSFET. A substrate 700 many include doped monocrystalline silicon having various diffusion regions (not shown) formed therein. Further, an isolation structure 703 may be formed in a substrate 700. A conducting structure 702 may include doped polycrystalline silicon, (xe2x80x9cpolyxe2x80x9d) having a layer of silicide formed thereon.
A conducting structure may further include a top insulating structure 704 and sidewalls 706. Sidewalls may be formed by the deposition of an insulating material and a subsequent anisotropic etch of the insulating material. As just one example, a top insulating structure 704 and sidewalls 706 may conventionally include silicon dioxide.
FIG. 7B shows an integrated circuit following the formation of a liner 708. A liner 708 may protect a substrate 700 and a conducting structure 702 from a subsequent etch, thereby serving as an etch stop layer for the subsequent etch. In particular, a liner may prevent substantial etching of a sidewall and/or an isolation structure within a substrate 700. Even more particularly, an isolation structure and a subsequently formed first insulating layer may both include silicon dioxide. Thus, an etch through a first insulating layer (such as a contact hole forming etch) may have no substantial selectivity with an isolation structure. Consequently, without a liner 708, such an etch may xe2x80x9cgougexe2x80x9d an isolation structure. Such gouging can result in leakage current that may adversely affect integrated circuit reliability and/or the characteristics circuit devices (such as transistors).
A liner may include silicone nitride. A drawback to a silicon nitride liner can be the temperature at which such a layer may be formed, which may increase a thermal budget.
FIG. 7C shows an integrated circuit following the formation of a first insulating layer 710. A first insulating layer 710 can insulate a substrate 700 and/or a conducting structure 702 from a subsequently formed contact and/or interconnect pattern. A first insulating layer may include BPSG deposited by a plasma enhanced chemical vapor deposition (PECVD) step.
BPSG may be selected as a conventional choice for a first insulating material due to its low xe2x80x9creflowxe2x80x9d temperature. Reflow involves heating a layer so that the layer becomes more malleable, and thus flows to fill in the lowest lying space. The reflowed layer may thus become more planar than the originally deposited layer. A reflow step may also add to the thermal budget of a manufacturing process.
Generally, the higher the concentration of boron and phosphorous, the lower the reflow temperature of the BPSG. BPSG is also desirable in that it can be a getterer for undesirable mobile ions, such as sodium, that can result in reliability failures in integrated circuits. Unfortunately, BPSG can have undesirable properties as well. The boron ions within BPSG can out-diffuse from the BPSG into the substrate, unintentionally doping the substrate. In addition, boron dopants can out-diffuse into polysilicon lines, unintentionally lowering or raising the conductivity of such lines.
While BPSG provides a relatively lows reflow temperature, there are limits to BPSG reflow temperatures. Such limits arise out of the adverse effects presented by highly doped BPSG. Relatively high concentrations of boron (e.g., over 5% by weight) may make the resulting BPSG film unstable and hygroscopic (attract moisture). Unstable BPSG can crack and/or form boron rich crystals. BPSG cracks can ruin the insulating properties of the BPSG, while boron rich crystals may result in non-planar surfaces and/or micro-masking etch defects. The hygroscopic nature of conventional high-concentration BPSG can create bubbles, or result in forming one or more phosphorous-based acids. Which may corrode conductive lines, such as those containing aluminum.
A BPSG layer may also be densified. A densification step may by incorporated into a reflow step or occur prior to, or after a reflow step. Densification can increase the stability of an insulating layer. Densification may be accomplished by raising the temperature of a BPSG layer following its deposition. Thus, densification of a BPSG may also contribute to the thermal budget of a process.
Another insulating material is phosphorous doped glass (phosphosilicate glass, or xe2x80x9cPSGxe2x80x9d). PSG is generally not used in conventional approaches due to its higher flow temperature. The flow temperature can be lowered by increasing the concentration of phosphorous, but higher concentrations of conventional PSG may have the drawbacks discussed above, including the formation of bubbles and/or acids. Accordingly, conventional PSG approaches may not be used as first insulating layer as such approaches can result in a higher thermal budget than those that include BPSG.
A first insulating layer 710 may also be planarized. An integrated circuit following a planarization step is shown in FIG. 7D. A planarization step may include chemical-mechanical polishing (CMP).
Following a planarization step a xe2x80x9ccapxe2x80x9d insulating layer 712 may be formed over a first insulating layer 710. A cap insulating layer 712 may serve to prevent the migration of dopants within a first insulating layer 710 and/or prevent moisture from migrating into a first insulating layer 710. A cap insulating layer 712 may also provide a more stable surface for subsequent layers. A conventional cap insulating layer 712 may include undoped silicon dioxide. An integrated circuit following the formation of a cap insulating layer is shown in FIG. 7E.
FIG. 7F shows an integrated circuit following the formation of a contact etch mask 714. A contact etch mask 714 may he formed with conventional photolithographic techniques, and include developed photoresist with mask openings 716 that can expose portions of a cap insulating layer 712.
With a contact etch mask 714 formed over a cap insulating layer 712 and first insulating layer 710, a contact hole 718 may be etched to a substrate 700 that is self-aligned with respect to a conductive structure 702. In the event a cap insulating layer 712 and first insulating layer 710 are undoped silicon dioxide and BPSG, respectively, a formation of contact hole may include a two step etch process. A first etch may be optimized for removal of undoped silicon dioxide and a second etch may be optimized for the removal of BPSG. An integrated circuit following the formation of a contact hole is shown in FIG. 7G.
An etch that forms a contact hole 718 through a first insulating layer 710 and/or a cap insulating layer 712 may be selective between a liner 708 and a first insulating layer 710. As shown in FIG. 7G, following such an etch, a liner 708 may remain substantially intact, and protect a substrate 700, and/or a sidewall 706, and/or a top insulating structure 704 from such a contact etch. In the event a first insulating layer 710 includes BPSG and a liner 708 includes silicon nitride, such an etch may be all xe2x80x9coxidexe2x80x9d etch. An oxide etch may etch a layer of silicon dioxide or doped silicon dioxide at a substantially faster rate than a layer of silicon nitride.
A liner etch may then remove portions of a liner 708. An integrated circuit following a liner etch is shown in FIG. 7H. A liner opening 720 may be formed, exposing a portion of a substrate 700 forming a contact area. However, a contact area width, shown by measuring bar 722, may be limited by residual portions of a liner 708.
As feature sizes in ICs continue to shrink, conventional approaches to forming contacts may only provide limited results. It would be desirable to arrive at some way of increasing contact area over conventional approaches, such as that shown in FIGS. 7A to 7H.
It would also be desirable to reduce the thermal budget of an IC manufacturing process. Such a reduction may result in more reliable devices and smaller IC features.
It would also be desirable to reduce the number of steps in an IC manufacturing process. Such a reduction may result in faster cycle times, provide a simpler process and accrue the various other benefits thereof.
The various disclosed embodiments set forth methods of forming self-aligned contacts. Such methods may form contacts with features that are less than 0.20 microns (xcexcm) without forming a liner to protecting lower conducting structure, such as a substrate and/or a transistor gate.
According to one aspect of the embodiments, self-aligned contacts may be formed in a first insulating layer that is not densified.
According to another aspect of the embodiments, a first insulating layer may include phosphosilicate glass (PSG).
According to another aspect of the embodiments, contacts may be formed to a substrate through a first insulating layer that includes silicon dioxide. Such contacts are self-aligned with respect to a transistor gate having a silicon nitride sidewall formed thereon.
According to another aspect of the embodiments, contacts may be formed that are self-aligned with two conductive structures separated from one another by 0.30 xcexcm or less. A contact feature may be greater than 0.05 xcexcm.
An advantage of one or more of the disclosed embodiments is that a small geometry contact may be formed without a protective liner.
Another advantage of one or more of the disclosed embodiments is that a method of forming self-aligned contacts may have a smaller thermal budget and/or fewer steps than conventional methods by not including a liner formation step.
Another advantage of one or more of the disclosed embodiments is that a method of forming self-aligned contacts through a first insulating layer may have a smaller thermal budget and/or fewer steps than conventional methods by not including a densification step for a first insulating layer.